Frame Mode Overview
Frame mode lets independent RTL designs share one chip top and one physical IO bank. It is a hardware structure implemented by FrameTop, covering design selection, clock and reset isolation, and bidirectional IO multiplexing.
一个物理 IO 边界，多个隔离设计
user_io[72:0]Three boundaries
| Boundary | Purpose | User editable |
|---|---|---|
FrameTop | Chip top that selects a design and connects physical IO | No |
UserDesign* | Uniform wrapper interface for user RTL | Module body only |
designs/<name>/ | Sources, manifest, and tests for one design | Yes |
Every design receives clock, reset, io_in[65:0], io_out[65:0], and io_oe[65:0]. Setting io_oe[n] to one drives payload pad n; clearing it releases the pad so it can be read as an input.
IO groups
user_io[6:0] -> 7-bit design ID for 128 possible slots
user_io[72:7] -> 66-bit payload for the selected design
design io_*[n] <-> external user_io[n + 7]The ID pins select a slot and are not part of the user payload. See IO Mapping for the complete mapping.
Selection sequence
T0保持复位reset = 1，所有用户槽位保持隔离。T1提供编号在 user_io[6:0] 放置目标 design ID。T2锁存选择FrameTop 同步并确认有效槽位。T3释放复位仅选中设计获得时钟、复位释放和 payload。Hold reset active, place the design ID on user_io[6:0], wait for selection to settle, and then release reset. Changing the pins while running does not switch designs immediately. Enter reset again to select a different slot. See Design Selection, Clock, and Reset Control.
Isolation
Only the selected design receives a running clock, released reset, and access to the payload IO mux. Every other slot remains clock-gated, held in reset, and high impedance. An ID absent from the registry leaves all user slots isolated. Design 0 is the fixed reference SoC; slots 1 through 127 are user designs.
IDs during user development
A design ID identifies a final chip slot, not a user's package. A user normally has one unregistered package and only needs:
make user-checkThe FrameTop test creates a temporary registry below build/ and assigns a test slot automatically. A maintainer assigns the permanent ID during integration. See the user guide and registration notes.
Finding a design in waveforms
After generating an FST with TRACE=1, inspect selection_valid, the relevant bit of design_selected, and payload_in/payload_out/payload_oe. Then descend into u_design_registry.u_design_<id> for the wrapper's IO and internal state.
A bidirectional pad reads back the resolved line value, so io_in can contain both external inputs and values currently driven by the selected design. This is normal. See Simulation and Regression for waveform commands and contention checks.