RISC-V SoC workspace

mpc-soc

A simulatable RISC-V SoC board. Attach a core to an existing slot, run software, and inspect the memory map from one documentation workbench.

Open the user guide

TOPasicTop

CLOCK50 MHz

DATA32 bit

RESET PC0x3000_0000

Verilator 5.050

SOC DATA PATH

一个 AXI master，一组可仿真外设

asicTop / SimTop

RISC-V core slotCORE_SEL 选择待测 CPU

AXI4 XBarAXI4 → APB4 外设互连

Flash / PSRAMXIP + 24 MiB 软件窗口

SimTop board modelsUART · GPIO · SPI · I2C

selected coreclock on · reset off

other CORE_SEL slotsheld in reset

memory interconnect unused slots

Documentation

Get the User KitClone the CI-tested user release User guideAttach a core and run SoC simulation ArchitectureasicTop, SimTop, and the AXI fabric Memory mapFlash, PSRAM, and peripheral windows IP readinessSmoke status and verification limits

Quick start

mpc-soc

$ make doctor
$ make check
SOC SMOKE CHECK PASS

Users attach a core through CORE_SEL. Full bootrom regression stays on the maintainer Makefile.

IP readiness

IP	Function	Address	Status	Tests	Gaps
CPU core	Runs RISC-V software, issues AXI traffic, and takes interrupts	core slot 0, default CORE_SEL=0	smoke-pass	SoC boot, basic software	instruction completeness, exceptions/privilege, performance, long runs
CLINT	Software interrupt, timer interrupt, mtime/mtimecmp	0x0201_0000	smoke-pass	clint	multi-hart semantics, races, timing corners
PLIC	External interrupt aggregation, priority, and delivery	0x0c00_0000	smoke-pass	plic	concurrent sources, priority corners, stress
UART0 / UART16550	Console UART, 16550 registers and FIFO	0x1000_0000	smoke-pass	uart_poll, UART input	baud corners, overflow, error frames, sustained traffic
SPI	SPI flash interface and XIP	Flash: 0x3000_0000	smoke-pass	flash_xip, boot fetch	real-device timing, erase/program, power-loss, compatibility
RCU	Clock select, divide, and reset control	0x1000_2000	smoke-pass	rcu	dynamic switching, reset timing, clock gating
RTC	Real-time clock count	0x1000_4000	smoke-pass	rtc	calibration, low power, CDC, long-term drift
WDG	Watchdog count, timeout, and reset	0x1000_5000	smoke-pass	wdg	reset races, clock faults, system recovery
ArchInfo	Architecture and chip information registers	0x1000_6000	smoke-pass	archinfo	configuration compatibility, full read-only checks
GPIO	GPIO input, output, and direction	0x1010_0000	smoke-pass	gpio, gpio_toggle	direction changes, edges/interrupts, pad electricals
UART1	APB4 UART transmit and receive	0x1010_3000	smoke-pass	uart1	corners, errors, and interrupt cases
I2C	I2C host controller and open-drain interface	0x1010_4000	smoke-pass	i2c	multi-slave, arbitration, ACK/NACK, bus recovery
PWM	Four PWM outputs	0x1010_6000	smoke-pass	pwm	frequency/duty corners, live reconfig, jitter
Timer	APB timers, four instances	0x1010_8000 - 0x1010_b000	smoke-pass	timer, timer_multi	overflow, restart, concurrency, interrupt corners
QSPI	Quad SPI controller	0x1020_0000	smoke-pass	qspi	real transfers, mode/clock, flash compatibility
RNG	Pseudo-random generation	0x1030_0000	smoke-pass	rng	statistics, seed and period; not a secure RNG
CRC	CRC8/CRC16/CRC32 calculation	0x1030_1000	smoke-pass	crc	full parameter combinations, streaming data, edge lengths
PSRAM controller	Three PSRAM chips, 24 MiB total	0xc000_0000	smoke-pass	psram_basic	real timing, bandwidth, refresh, PVT, long stress

Memory map

20 mapped regions

memoryflash0x3000_0000

External SPI flash XIP window. · 0x0100_0000

memorypsram0xC000_0000

External PSRAM window, three 8MiB chips. · 0x0180_0000

peripheralclint0x0201_0000

Core-local interruptor. · 0x0001_0000

peripheralplic0x0C00_0000

Platform-level interrupt controller. · 0x0040_0000

peripheraluart00x1000_0000

UART16550 console. · 0x0000_1000

peripheralrcu0x1000_2000

Reset and clock control unit. · 0x0000_1000

peripheralrtc0x1000_4000

Real-time clock. · 0x0000_1000

peripheralwdg0x1000_5000

Watchdog timer. · 0x0000_1000

peripheralarchinfo0x1000_6000

Architecture information registers. · 0x0000_1000

peripheralgpio00x1010_0000

GPIO controller. · 0x0000_1000

peripheraluart10x1010_3000

APB4 UART controller. · 0x0000_1000

peripherali2c0x1010_4000

APB4 I2C controller. · 0x0000_1000

peripheralpwm0x1010_6000

PWM controller. · 0x0000_1000

peripheraltimer00x1010_8000

APB timer. · 0x0000_1000

peripheraltimer10x1010_9000

APB timer. · 0x0000_1000

peripheraltimer20x1010_A000

APB timer. · 0x0000_1000

peripheraltimer30x1010_B000

APB timer. · 0x0000_1000

peripheralqspi0x1020_0000

APB4 QSPI controller. · 0x0000_1000

peripheralrng0x1030_0000

Pseudo-random number generator. · 0x0000_1000

peripheralcrc0x1030_1000

CRC calculation engine. · 0x0000_1000